1. Field of the Invention
The present invention relates in general to data signal distribution circuits for synchronous memory devices, and more particularly to a data signal distribution circuit for a synchronous memory device which is capable of accurately distributing successive data signals from a data generation source to at least two peripheral circuits, the data generation source being driven in response to an external clock signal.
2. Description of the Prior Art
Generally, a data signal distribution circuit for a synchronous memory device is adapted to generate internal address signals for designating at least two peripheral circuits to which successive data signals from a data generation source are to be transmitted. The data signal distribution circuit also controls a multiplexer for distributing the successive data signals from the data generation source to said at least two peripheral circuits in response to the internal address signals. However, the data signal distribution circuit generates the internal address signals in response to an external clock signal, thereby causing the internal address signals not to be synchronized with the successive data signals from the data generation source. For this reason, the data signal distribution circuit cannot accurately distribute the successive data signals from the data generation source to said at least two peripheral circuits. Such a problem with the data signal distribution circuit will hereinafter be described in detail with reference to FIGS. 1 to 3.
Referring to FIG. 1, there is shown the construction of a conventional data signal distribution circuit for a synchronous memory device. As shown in this drawing, the conventional data signal distribution circuit comprises a data generator 10 for generating successive data signals in response to a clock signal from a first control line 11 as shown in FIG. 2A, and an internal address generator 12 for inputting the clock signal from the first control line 11 and an external address signal from a second control line 13 as shown in FIG. 2D.
Preferably, the data generator 10 must generate a data signal string delayed for an interval shorter than a period of the clock signal from the first control line 11, as shown in FIG. 2B. However, the data generator 10 generates a data signal string delayed for an interval longer than the period of the clock signal from the first control line 11, as shown in FIG. 2C.
The internal address generator 12 is adapted to decode the clock signal from the first control line 11 and the external address signal from the second control line 13 to generate first and second internal address signals. To this end, the internal address generator 12 includes a NAND gate G1 and an inverter I2, for generating the first internal address signal, which is high in logic when the clock signal from the first control line 11 and the external address signal from the second control line 13 are both high in logic. The NAND gate G1 and the inverter I2 constitute a decoder. Also, the internal address generator 12 includes two inverters I1 and I3 and a NAND gate G2, for generating the second internal address signal, which is high in logic when the clock signal from the first control line 11 is high in logic and the external address signal from the second control line 13 is low in logic. Similarly, the inverters I1 and I3 and the NAND gate G2 constitute a decoder.
The conventional data signal distribution circuit further comprises a strobe signal generator 14 for generating a strobe signal in response to the clock signal from the first control line 11, and a clock controller 20 for transferring the strobe signal from the strobe signal generator 14 to a multiplexer 22 in response to the first and second internal address signals from the internal address generator 12.
The strobe signal generator 14 comprises a first delay circuit 16 for delaying the clock signal from the first control line 11 for a predetermined time period, and a second delay circuit 18, a NAND gate G3 and two inverters I4 and I5, for generating the strobe signal in response to the delayed clock signal from the first delay circuit 16, which has a predetermined high logic pulse width beginning with a rising edge of the delayed clock signal from the first delay circuit 16. The second delay circuit 18, the NAND gate G3 and the inverters I4 and I5 constitute an edge detector. Preferably, the strobe signal from the strobe signal generator 14 must have a pulse train delayed for an interval shorter than the period of the clock signal from the first control line 11, as shown in FIG. 2E. However, the strobe signal from the strobe signal generator 14 has a pulse train delayed for an interval longer than the period of the clock signal from the first control line 11, as shown in FIG. 2F. This reason is that the first delay circuit 16 in the strobe signal generator 14 delays the clock signal from the first control line 11 by a propagation delay time of the data generator 10.
The clock controller 20 is adapted to generate a first switching clock signal which is high in logic when the first internal address signal from the internal address generator 12 and the strobe signal from the strobe signal generator 14 are both high in logic. To this end, the clock controller 20 includes a NAND gate G4 and an inverter I6 constituting a decoder. The clock controller 20 is also adapted to generate a second switching clock signal which is high in logic when the second internal address signal from the internal address generator 12 and the strobe signal from the strobe signal generator 14 are both high in logic. To this end, the clock controller 20 includes a NAND gate G5 and an inverter I7 constituting a decoder.
The multiplexer 22 is adapted to multiplex the successive data signals from the data generator 10 to first and second output lines 15 and 17 in response to the first and second switching clock signals from the clock controller 20. To this end, the multiplexer 22 includes a first control switch for transferring the data signals from the data generator 10 to the peripheral circuit (not shown) connected to the first output line 15 when the first switching clock signal from the clock controller 20 is high in logic. The multiplexer 22 also includes a second control switch for transferring the data signals from the data generator 10 to the peripheral circuit (not shown) connected to the second output line 17 when the second switching clock signal from the clock controller 20 is high in logic. The first control switch is provided with an NMOS transistor Q1 and a PMOS transistor Q2 connected in parallel to each other and an inverter I8 connected between a gate of the NMOS transistor Q1 and a gate of the PMOS transistor Q2. The second control switch is provided with an NMOS transistor Q3 and a PMOS transistor Q4 connected in parallel to each other and an inverter I9 connected between a gate of the NMOS transistor Q3 and a gate of the PMOS transistor Q4.
Preferably, the first control switch in the multiplexer 22 must transfer first and third data signals d1 and d3 from the data generator 10 to the first output line 15 at first and third periods of the clock signal from the first control line 11, respectively, as shown in FIG. 2G. However, the first control switch in the multiplexer 22 does not transfer the first data signal d1 from the data generator 10 to the first output line 15 at the first period of the clock signal from the first control line 11 but at a second period of the clock signal, as shown in FIG. 2H. Also, preferably, the second control switch in the multiplexer 22 must transfer a second data signal d2 from the data generator 10 to the second output line 17 at the second period of the clock signal from the first control line 11, as shown in FIG. 2I. However, the second control switch in the multiplexer 22 does not transfer the second data signal d2 from the data generator 10 to the second output line 17 at the second period of the clock signal from the first control line 11 but the third period of the clock signal, as shown in FIG. 2J.
Referring to FIG. 3, there is shown the construction of an alternative embodiment of the internal address generator 12 in FIG. 1. As shown in this drawing, the internal address generator 12 is provided with a 1 bit counter for counting the clock signal from the first control line 11 while an enable signal from a third control line 19 is high in logic. As a result of the counting operation, the 1 bit counter generates first and second internal address signals with the opposite logic levels. To this end, the 1 bit counter includes two NAND gates G6 and G7, two NMOS transistors Q5 and Q8, two PMOS transistors Q6 and Q7 and six inverters I10-I15.
As mentioned above, in the conventional data signal distribution circuit for the synchronous memory device, the internal address signals from the internal address generator 12 are not synchronized with the successive data signals from the data generator 10. For this reason, the conventional data signal distribution circuit cannot accurately distribute the successive data signals from the data generator 10 to the peripheral circuits.